Interrupt Handling Quiz Do you have a handle on Interrupts? Take this quiz to test your understanding in Interrupt Handling in Operating Systems! michelle published on April 12, 20230 responses 0 « Previous Next » Questions in vertical order 1/14 In which stage does the CPU respond to an interruption? Fetch-Execution cycle Instruction decoding Execution Interrupt acknowledge 2/14 Which of the following is NOT a type of interruption? Hint: 2 choices Hardware Interruption Software Interruption Hardware Polling Software Polling 3/14 Which of the following statement(s) is/are true about Interrupt Vectors? Hint: 2 choices They contain information about the interrupting device. They contain information about privilege levels of the instructions. They contain information about the device interruption handler. They contain information about the number of memory accounts used for a particular program 4/14 What is an Interrupt Controller? A register containing information about the number of memory accounts used for a particular program A hardware device that acts as an intermediary between the CPU and other hardware devices, enabling the processors to handle multiple interrupts A register containing information about privilege levels of the instructions. A special program that is executed in an interrupt acknowledge stage. 5/14 What is the purpose of an Interrupt Vector Table (IVT)? To contain information about the interrupting device To identify the entry point of the interrupt service routine (ISR) To provide privilege levels for the instructions To manage the memory accounts used for a particular program 6/14 What types of information is found in the Interrupt Vector Table Register (IVTR)? The size of the memory accounts used for a particular program The privilege levels of instructions The starting address of the IVT The interrupting devices information 7/14 What are the main purposes of the Interrupt Service Routines (ISRs)? Hint: 2 choices To save the CPU state before switching to the interrupt handler To allow the CPU to run in supervised mode To identify the entry point of the interrupt handler To provide privilege levels for the instructions 8/14 Which of the following statement(s) is/are true about software interrupts? Hint: 2 choices They are generated by the software using instructions They occur due to environmental conditions They are caused by an external device They require writing ISRs 9/14 What are the two major types of interrupt latency? Hardware interrupt latency and software interrupt latency Modified latency and conventional latency Direct latency and indirect latency Early latency and late latency 10/14 Which of the following statement(s) is/are true about advanced interrupt controller? Hint: 2 choices It can prioritize interrupts It can control the flow of data between hardware and software It can prioritize tasks It can route multiple interrupts to the same handler 11/14 Which of the following statement(s) is/are true about Programmable Interrupt Controller (PIC)? Hint: 2 choices It is an advanced interrupt controller It allows multiple processors to handle multiple interrupts It is a type of memory-mapped I/O device It provides the ability to prioritize interrupts 12/14 What is the purpose of an interrupt service routine (ISR)? Hint: 2 choices To execute a particular task upon an interrupt To handle the interrupts generated by the processor To save the previous CPU state To manage the memory accounts used for a particular program 13/14 What is the primary advantage of using Interrupt Handling in Operating Systems? Increasing speed of the system Better utilization of hardware resources Allowing multiple interrupts to be serviced simultaneously Efficient memory usage 14/14 Which of the following statement(s) is/are true about the APIC (Advanced Programmable Interrupt Controller)? Hint: 2 choices It is a special-purpose microprocessor used for interrupt handling It runs its own special operating systems software It allows multiple interrupts to be serviced simultaneously It routes multiple interrupts to the same handler
